Reception device, transmission device, communication system, signal reception method, signal transmission method, and communication method

ABSTRACT

There is provided a reception device including a data signal receiver circuit, a clock signal receiver circuit, and a discrimination circuit. The data signal receiver circuit receives a data signal through a data signal line, and receives a data blanking signal through the data signal line in a blanking period of the data signal. The clock signal receiver circuit receives a clock signal and a clock blanking signal through a clock signal line, the clock blanking signal outputted in synchronization with the blanking period of the data signal. The discrimination circuit discriminates communication modes on a basis of one or both of a signal value of the data blanking signal and a signal value of the clock blanking signal.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Japanese Priority PatentApplication JP 2016-084406 filed Apr. 20, 2016, the entire contents ofeach which is incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to a reception device, a transmissiondevice, a communication system, a signal reception method, a signaltransmission method, and a communication method that each are applied totransmission of a data signal and a clock signal.

BACKGROUND ART

In recent years, in association with increasing capacity of image datahandled by mobile devices such as smartphones and camera devices, higherspeed and lower power consumption of data transmission in a device orbetween different devices have been in demand. In order to meet suchdemands, standardization of high-speed interface specifications has beenpromoted. Examples of the high-speed interface specifications mayinclude the C-PHY specification and the D-PHY specification that havebeen developed as connection interface specifications for mobile devicesand camera devices by the Mobile Industry Processor Interface (MIPI)alliance. The C-PHY specification and the D-PHY specification areinterface specifications for communication protocol physical layers(PHY). Moreover, a display serial interface (DSI) for mobile devicedisplay or a camera serial interface (CIS) for camera device is providedas an upper protocol layer of the C-PHY specification or the D-PHYspecification.

CITATION LIST Patent Literature

PTL 1: Japanese Unexamined Patent Application Publication (PublishedJapanese Translation of PCT Application) No. JP 2014-522204

SUMMARY Technical Problem

In the above-described specifications such as the D-PHY specification,it may be expected that a plurality of communication modes will be mixedin each of a blanking period and a substantial data signal transmissionperiod in future. Accordingly, it may be necessary to discriminate theplurality of communication modes.

It is therefore desirable to provide a reception device, a transmissiondevice, a communication system, a signal reception method, a signaltransmission method, and a communication method that each make itpossible to easily discriminate a plurality of communication modes.

Solution to Problem

A reception device according to an embodiment of the present disclosureincludes a data signal receiver circuit, a clock signal receivercircuit, and a discrimination circuit. The data signal receiver circuitreceives a data signal through a data signal line, and receives a datablanking signal through the data signal line in a blanking period of thedata signal. The clock signal receiver circuit that receives a clocksignal and a clock blanking signal through a clock signal line, theclock blanking signal outputted in synchronization with the blankingperiod of the data signal. The discrimination circuit discriminatescommunication modes on a basis of one or both of a signal value of thedata blanking signal and a signal value of the clock blanking signal.

A transmission device according to an embodiment of the presentdisclosure includes a data signal transmitter circuit, a clock signaltransmitter circuit, and a blanking controller. The data signaltransmitter circuit outputs a data signal to a data signal line, andoutputs a data blanking signal through the data signal line in ablanking period of the data signal. The clock signal transmitter circuitthat outputs a clock signal to a clock signal line, and outputs a clockblanking signal, in place of the clock signal, in synchronization withthe blanking period of the data signal. The blanking controller controlsone or both of a signal value of the data blanking signal and a signalvalue of the clock blanking signal to a value that enablesdiscrimination of communication modes.

A communication system according to an embodiment of the presentdisclosure includes a transmission device and a reception device. Thetransmission device includes a data signal transmitter circuit, a clocksignal transmitter circuit and a blanking controller. The data signaltransmitter circuit outputs a data signal to a data signal line, andoutputs a data blanking signal through the data signal line in ablanking period of the data signal. The clock signal transmitter circuitoutputs a clock signal to a clock signal line, and outputs a clockblanking signal, in place of the clock signal, in synchronization withthe blanking period of the data signal. The blanking controller controlsone or both of a signal value of the data blanking signal and a signalvalue of the clock blanking signal to a value that enablesdiscrimination of communication modes. The reception device includes adata signal receiver, a clock signal receiver circuit, and adiscrimination circuit. The data signal receiver circuit receives thedata signal and the data blanking signal through the data signal line.The clock signal receiver circuit receives the clock signal and theclock blanking signal through the clock signal line. The discriminationcircuit discriminates the communication modes on a basis of one or bothof the signal value of the data blanking signal and the signal value ofthe clock blanking signal.

A signal reception method according to an embodiment of the presentdisclosure includes: receiving a data signal through a data signal line,and receiving a data blanking signal through the data signal line in ablanking period of the data signal; receiving a clock signal and a clockblanking signal through a clock signal line, the clock blanking signaloutputted in synchronization with the blanking period of the datasignal; and discriminating communication modes on a basis of one or bothof a signal value of the data blanking signal and a signal value of theclock blanking signal.

A signal transmission method according to an embodiment of the presentdisclosure includes: outputting a data signal to a data signal line, andoutputting a data blanking signal through the data signal line in ablanking period of the data signal; outputting a clock signal to a clocksignal line, and outputting a clock blanking signal, in place of theclock signal, in synchronization with the blanking period of the datasignal; and controlling one or both of a signal value of the datablanking signal and a signal value of the clock blanking signal to avalue that enables discrimination of communication modes.

A communication method according to an embodiment of the presentdisclosure includes: outputting a data signal to a data signal line, andoutputting a data blanking signal through the data signal line in ablanking period of the data signal; outputting a clock signal to a clocksignal line, and outputting a clock blanking signal, in place of theclock signal, in synchronization with the blanking period of the datasignal; controlling one or both of a signal value of the data blankingsignal and a signal value of the clock blanking signal to a value thatenables discrimination of a communication mode; receiving the datasignal and the data blanking signal through the data signal line;receiving the clock signal and the clock blanking signal through theclock signal line; and discriminating the communication modes on a basisof one or both of the signal value of the data blanking signal and thesignal value of the clock blanking signal.

In the reception device or the communication system according to theembodiment of the present disclosure, or the signal reception method orthe communication method according to the embodiment of the presentdisclosure, the communication modes are discriminated on the basis ofone or both of the signal value of the data blanking signal and thesignal value of the clock blanking signal.

In the transmission device or the communication system according to theembodiment of the present disclosure or the signal transmission methodor the communication method according to the embodiment of the presentdisclosure, one or both of the signal value of the data blanking signaland the signal value of the clock blanking signal are controlled to avalue that enables discrimination of the communication modes.

Advantageous Effects of Invention

According to the reception device, the communication system, the signalreception mode, and the communication method of the respectiveembodiments of the present disclosure, the communication modes arediscriminated on the basis of one or both of signal value of the datablanking signal and the signal value of the clock blanking signal, whichmakes it possible to easily discriminate a plurality of communicationmodes.

According to the transmission device, the communication system, thesignal transmission method, and the communication method of therespective embodiments of the present disclosure, one or both of thesignal value of the data blanking signal and the signal value of theclock blanking signal are controlled to a value that enablesdiscrimination of the communication modes, which makes it possible toeasily discriminate a plurality of communication modes.

Note that effects described here are non-limiting. Effects achieved bythe technology may be one or more of effects described in thedisclosure.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are provided toprovide further explanation of the technology as claimed.

BRIEF DESCRIPTION OF DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the technology, and are incorporated in and constitutea part of this specification. The drawings illustrate embodiments and,together with the specification, serve to explain the principles of thetechnology.

FIG. 1 is a block diagram illustrating an outline of a communicationsystem that transmits a data signal and a clock signal.

FIG. 2 is a block diagram illustrating a configuration example of acommunication system according to a comparative example that implementsthe communication system illustrated in FIG. 1.

FIG. 3 is a circuit diagram illustrating a specific circuitconfiguration example of the communication system illustrated in FIG. 2.

FIG. 4 is an explanatory diagram illustrating an example of respectivesignal waveforms to be transmitted on a clock lane and a data lane inthe communication system illustrated in FIG. 2.

FIG. 5 is a block diagram illustrating an outline of a communicationsystem according to a first embodiment of the present disclosure.

FIG. 6 is a circuit diagram illustrating a specific circuitconfiguration example of the communication system according to the firstembodiment.

FIG. 7 is an explanatory diagram illustrating an example of acommunication mode (a blanking mode) in a blanking period.

FIG. 8 is an explanatory diagram illustrating an example of a framestructure of image data.

FIG. 9 is an explanatory diagram illustrating a first example ofrespective signal waveforms to be transmitted on a clock lane and a datalane in the communication system according to the first embodiment.

FIG. 10 is an explanatory diagram illustrating a second example ofrespective waveforms to be transmitted on the clock lane and the datalane in the communication system according to the first embodiment.

FIG. 11 is an explanatory diagram of a differential signal value.

FIG. 12 is a block diagram illustrating an outline of a communicationsystem according to a second embodiment.

FIG. 13 is a block diagram illustrating a specific application exampleof the communication system according to the second embodiment.

FIG. 14 is a flow chart illustrating an example of a data transmissionprocess in the application example illustrated in FIG. 13.

FIG. 15 is an explanatory diagram illustrating an example of data signalcommunication modes (data transmission modes).

FIG. 16 is an explanatory diagram illustrating a first example ofrespective waveforms to be transmitted on a clock lane and a data lanein a communication system according to a third embodiment.

FIG. 17 is an explanatory diagram illustrating an example of a method ofdiscriminating communication modes in the first example illustrated inFIG. 16.

FIG. 18 is an explanatory diagram illustrating a second example ofrespective waveforms to be transmitted on the clock lane and the datalane in the communication system according to the third embodiment.

FIG. 19 is an explanatory diagram illustrating an example of a method ofdiscriminating communication modes in the second example illustrated inFIG. 18.

FIG. 20 is an explanatory diagram illustrating a third example ofrespective waveforms to be transmitted on the clock lane and the datalane in the communication system according to the third embodiment.

FIG. 21 is an explanatory diagram illustrating an example of a method ofdiscriminating communication modes in the third example illustrated inFIG. 20.

FIG. 22 is a perspective view of an example of an appearanceconfiguration of a smartphone to which any of the communication systemsaccording to the respective embodiments is applied.

FIG. 23 is a block diagram illustrating a configuration example of anapplication processor to which any of the communication systemsaccording to the respective embodiments is applied.

FIG. 24 is a block diagram illustrating a configuration example of animage sensor to which any of the communication systems according to therespective embodiments is applied.

FIG. 25 is an explanatory diagram illustrating an installation exampleof a vehicle-mounted camera to which any of the communication systemsaccording to the respective embodiments is applied.

FIG. 26 is a block diagram illustrating a configuration example of thevehicle-mounted camera to which any of the communication systemsaccording to the respective embodiments is applied.

DESCRIPTION OF EMBODIMENTS

Some embodiments of the present disclosure are described in detail belowwith reference to the accompanying drawings. It is to be noted thatdescription is given in the following order.

0. Communication System Using LP Signal and HS Differential Signal(Comparative example) (FIGS. 1 to 4)

1. First Embodiment (Communication system having a blanking modediscriminating function and using only an HS differential signal) (FIGS.5 to 11)

2. Second Embodiment (Communication system that enables switchingbetween an LP signal and an HS differential signal) (FIGS. 12 to 14)

3. Third Embodiment (Communication system having a data transmissionmode discriminating function) (FIGS. 16 to 21)

4. Application Examples

4.1 First Application Example (FIGS. 22 to 24)

4.2 Second Application Example (FIGS. 25 and 26)

5. Other Embodiments

0. COMMUNICATION SYSTEM USING LP SIGNAL AND HS DIFFERENTIAL SIGNAL

In general, in the C-PHY specification and the D-PHY specification, ahigh speed (HS) differential signal is used for substantial data signaltransmission. Moreover, a low power (LP) signal is used for blankingperiods of a clock signal and a data signal. The HS differential signaland the LP signal are transmitted on a common transmission path. Forexample, in the D-PHY specification, one transmission path (clock lane)where the clock signal is transmitted and one or more transmission paths(data lanes) where the data signal is transmitted may be provided. Asignal transmission period on each of the clock lane and the data laneincludes a period in which transmission using the HS differential signalis performed and a period in which transmission using the LP signal isperformed. On each of the clock lane and the data lane, the HSdifferential signal and the LP signal are transmitted on the commontransmission path. However, the LP signal is not a differential signalbut a single-ended signal, and is different in voltage value necessaryfor signal transmission from the HS differential signal. Hence, acircuit for transmission and reception of the HS differential signal anda circuit for transmission and reception of the LP signal are necessaryindependently.

First, description is given of an outline of a communication systemusing the LP signal and the HS differential signal as a comparativeexample before description of communication systems according toembodiments of the present disclosure.

FIG. 1 illustrates an outline of a communication system supporting acommunication interface by, for example, the C-PHY specification or theD-PHY specification. The communication system illustrated in FIG. 1includes a transmitter TX and a receiver RX. Moreover, the communicationsystem includes a clock lane CL and a data lane DL that are providedacross the transmitter TX and the receiver RX. The clock lane CL allowsa clock signal to be transmitted thereon. The data lane DL allows, forexample, a data signal such as image data to be transmitted thereon. Itis to be noted that FIG. 1 illustrates an example in which four datalanes LD1, DL2, DL3, and DL4 are provided as the data lanes DL; however,the number of data lanes is not limited thereto, and only one data laneDL1 may be provided.

The transmitter TX includes a transmission digital circuit TX-DIGITALand a transmission analog circuit TX-ANALOG. For example, a 16-bit or8-bit parallel signal may be transmitted between the transmissiondigital circuit TX-DIGITAL and the transmission analog circuitTX-ANALOG.

The receiver RX includes a reception digital circuit RX-DIGITAL and areception analog circuit RX-ANALOG. For example, a 16-bit or 8-bitparallel signal may be transmitted between the reception analog circuitRX-ANALOG and the reception digital circuit RX-DIGITAL on each of thedata lanes DL1, DL2, DL3, and DL4. For example, a 2-bit serial signalmay be transmitted between the reception analog circuit RX-ANALOG andthe reception digital circuit RX-DIGITAL on the clock lane CL.

The transmission analog circuit TX-ANALOG and the reception analogcircuit RX-ANALOG are coupled to each other by a clock signal line 30 onthe clock lane CL. The clock signal line 30 allows a differential clocksignal to be transmitted therethrough. The transmission analog circuitTX-ANALOG and the reception analog circuit RX-ANALOG are coupled to eachother by data signal lines 31, 32, 33, and 34 on the data lanes DL1,DL2, DL3, and DL4, respectively. Each of the data signal lines 31, 32,33, and 34A allows a differential data signal to be transmittedtherethrough. Each of the clock signal line 30 and the data signal lines31, 32, 33, and 34 includes a pair of a positive signal line Dp and anegative signal line Dn through which a differential signal istransmitted. For example, a 2-bit serial signal may be transmittedthrough each of the clock signal line 30 and the data signal lines 31,32, 33, and 34.

FIG. 2 illustrates a configuration example of a communication systemaccording to a comparative example that implements the communicationsystem illustrated in FIG. 1. It is to be noted that FIG. 2 illustratesonly one data lane DL1 as the data lane DL in FIG. 1; however, the otherdata lanes DL2, DL3, and DL4 may have a configuration substantiallysimilar to that of the data lane DL1.

The communication system according to this comparative example includesa transmitter 101 and a receiver 102. The transmitter 101 and thereceiver 102 respectively correspond to the transmitter TX and thereceiver RX in FIG. 1.

On the clock lane CL, the transmitter 101 includes a CL-HS circuit 111that processes the HS differential signal and a CL-LP circuit 112 thatprocesses the LP signal. On the data lane DL1, the transmitter 101includes a DL-HS circuit 113 that processes the HS differential signaland a DL-LP circuit 114 that processes the LP signal.

On the clock lane CL, the receiver 102 includes a CL-HS circuit 121 thatprocesses the HS differential signal and a CL-LP circuit 122 thatprocesses the LP signal. On the data lane DL1, the receiver 102 includesa DL-HS circuit 123 that processes the HS differential signal and aDL-LP circuit 124 that processes the LP signal.

FIG. 3 illustrates a specific circuit configuration example of thecommunication system according to the comparative example illustrated inFIG. 2. Moreover, FIG. 4 illustrates an example of respective signalwaveforms to be transmitted on the clock lane CL and the data lane DL1in the communication system according to the comparative exampleillustrated in FIG. 2.

In the communication system according to the comparative example, astatus of a signal to be outputted from the transmitter 101 to the clocksignal line 30 on the clock lane CL has a high speed state (HSP) periodand a low power state (LPS) period, as illustrated in FIG. 4. In the HSPperiod, the signal is in a state of being transmitted in the form of theHS differential signal. In the LPS period, the signal is in a state ofbeing transmitted in the form of the LP signal. A substantial clocksignal is outputted in the form of the HS differential signal in the HPSperiod.

Likewise, a status of a signal to be outputted from the transmitter 101to the data signal line 31 on the data lane CL has a high speed state(HSP) period and a low power state (LPS) period. In the HSP period, thesignal is in a state of being transmitted in the form of the HSdifferential signal. In the LPS period, the signal is in a state ofbeing transmitted in the form of the LP signal. A substantial datasignal is outputted in the form of the HS differential signal in the HPSperiod. It is to be noted that a substantial data signal portion isrepresented by “HST”. Moreover, the HPS period may include, for example,a TRAIL period T_(HS-TRAIL) and a SYNC (synchronization) periodT_(HS-SYNC). A blanking period not including the substantial data signalportion is included in the LPS period. The substantial data signal maybe outputted in a byte unit, for example.

The communication system includes a crystal oscillator (XTAL) 82, a PLLcircuit 81, and a crystal oscillator (XTAL) 83, as illustrated in FIG.3. The crystal oscillator (XTAL) 82 and the PPL circuit 81 each supplythe clock signal to respective circuit sections in the transmitter 101.The crystal oscillator (XTAL) 83 supplies the clock signal to respectivecircuit sections in the receiver 102.

The CL-HS circuit 111 includes an HS state machine (HS FSM) 51, aselector 52, a parallel-serial (PS) conversion circuit 53, a clockfrequency divider (DIV) 54, and an HS driver (HS DRV) 55. The selector52 selectively outputs a Toggle signal, a signal with a value of 0(ALL0), and a signal with a value of 1 (ALL1). The Toggle signal may bean 8-bit clock signal (1010_1010), for example.

The CL-LP circuit 112 includes an LP state machine (LP FSM) 41, an LPencoder (LP ENC) 42, and an LP driver (LP DRV) 43. A clock lane controlsignal is inputted to the LP state machine 41.

The DL-HS circuit 113 includes an HS state machine (HS FSM) 71, aselector 72, a parallel-serial (PS) conversion circuit 73, and an HSdriver (HS DRV) 74. A data transmission ready signal TxReadyHS isoutputted from the HS state machine 71. The selector 72 selectivelyoutputs transmission data TxDataHS, a synchronization code signal SYNC,the signal with a value of 0 (ALL0), and the signal with a value of 1(ALL1).

The DL-LP circuit 114 includes an LP state machine (LP FSM) 61, an LPencoder (LP ENC) 62, and an LP driver (LP DRV) 63. A data transmissionrequest signal TxRequestHS is inputted to the LP state machine 61.

It is to be noted that the LP driver 43, the HS driver 55, the LP driver63, and the HS driver 74 in the transmitter 101 correspond to thetransmission analog circuit TX-ANALOG in FIG. 1.

The CL-HS circuit 121 includes a termination circuit (TERM) 56 servingas a clock signal termination circuit, an HS receiver (HS RCV) 57, and aclock frequency divider (DIV) 58. The termination circuit 56 includes aterminator.

The CL-LP circuit 122 includes an LP receiver (LP RCV) 44, an LP decoder(LP DEC) 45, and an LP state machine (LP FSM) 46. The LP state machine46 outputs a status signal of the clock lane CL.

The DL-HS circuit 123 includes a termination circuit (TERM) 75 servingas a data signal termination circuit, an HS receiver (HS RCV) 76, aclock frequency divider (DIV) 77, and a word alignment correctioncircuit (ALN) 78. The termination circuit 75 includes a terminator. Theword alignment correction circuit (ALN) 78 outputs a receptionsynchronization signal RxSyncHS, a reception valid signal RxValidHS, andreception data RxDataHS.

The DL-LP circuit 124 includes an LP receiver (LP RCV) 64, an LP decoder(LP DEC) 65, and an LP state machine (LP FSM) 66. The LP state machine66 outputs a reception active signal RxActiveHS.

It is to be noted that mainly the LP receiver 44, the terminationcircuit 56, the HS receiver 57, the LP receiver 64, the terminationcircuit 75, and the HS receiver 76 in the receiver 102 correspond to thereception analog circuit RX-ANALOG in FIG. 1.

1. FIRST EMBODIMENT

Next, description is given of a first embodiment of the presentdisclosure. Hereinafter, description of configurations and workingssubstantially similar to those in the foregoing comparative example isomitted.

FIG. 5 illustrates an outline of a communication system according to thefirst embodiment of the present disclosure that implements thecommunication system illustrated in FIG. 1. FIG. 6 illustrates aspecific circuit configuration example of the communication systemillustrated in FIG. 5. It is to be noted that FIG. 5 and other drawingsillustrate only one data lane DL1 as the data lane DL in FIG. 1;however, the other data lanes DL2, DL3, and DL4 may have a configurationsubstantially similar to that of the data lane DL1.

The communication system according to the present embodiment includes atransmitter 1 (a transmission device) and a receiver 2 (a receptiondevice). The transmitter 1 and the receiver 2 respectively correspond tothe transmitter TX and the receiver RX in FIG. 1. The transmitter 1includes a blanking controller 20.

The communication system according to the comparative exampleillustrated in FIGS. 2 to 4 uses a communication mode in which an LPsignal having a voltage of about 1.3 V is outputted in the blankingperiods of the clock signal and the data signal. However, it has becomedifficult to keep this voltage in association with advances insemiconductor process.

Accordingly, in the communication system according to the presentembodiment, on the clock lane CL, all signals to be outputted from thetransmitter 1 to the clock signal line 30 including the blanking periodare HS differential signals only. Likewise, on the data lane DL1, allsignals to be outputted from the transmitter 1 to the data signal line31 including the blanking period are HS differential signals only.

Moreover, the communication system according to the present embodimenthas a plurality of communication modes (blanking modes) in the blankingperiod.

FIG. 7 illustrates an example of blanking modes in the presentembodiment. In the present embodiment, examples of the blanking modesmay include a first blanking mode in which a transmission period isrelatively short and a second blanking mode in which a transmissionperiod is relatively long.

The first blanking mode is a communication (Latency Reduction TransportEfficiency: LRTE) mode in which a blanking interval is minimized. In theLRTE mode, the transmission period has a fixed length. Moreover, theLRTE mode is a mode in which termination control is not performed(on-off switching of a terminator is not performed).

The second blanking mode is a communication (Alternate LP: ALP) modesuitable for a long blanking period. In the ALP mode, the transmissionperiod has a variable length. Moreover, the ALP mode is a mode in whichit is possible to perform termination control (on-off switching of theterminator is possible).

FIG. 8 illustrates an example of a frame structure of image data to betransmitted in the communication system according to the presentembodiment. FIG. 8 illustrates a frame structure of two frames of imagedata. A header of the frame is referred to as “FS (frame start)”, and afooter of the frame is referred to as “FE (frame end)”. An intervalbetween the two frames is a frame blanking period (vertical blankingperiod) Vb. In one frame, a header of one horizontal period is referredto as “packet header”, and a footer of the one horizontal period isreferred to as “PF (packet footer)”.

A data signal may be inserted into a horizontal blanking period Hb.Examples of the data signal may include a phase difference detectiondata PDAF (Phase Detection Auto-Focus) used for phase-differenceauto-focusing. In the horizontal blanking period Hb, a period Hb1excluding a period Hb2 into which the data signal such as PDAF (PhaseDetection Auto-Focus) is inserted is a substantial horizontal blankingperiod. In this case, the horizontal blanking period Hb1 is extremelyshort. Accordingly, in the communication system according to the presentembodiment, the first blanking mode (the LRTE mode) is suitable as theblanking mode for communication in the horizontal blanking period Hb1.Moreover, the second blanking mode (the ALP mode) is suitable forcommunication in the vertical blanking period Vb.

In a case in which a plurality of communication modes are mixed in theblanking period in such a manner, it is necessary to discriminate theplurality of communication modes in the receiver 2. One possiblediscrimination technique is to measure a length of a period in which theclock signal is stopped. However, in this case, it is necessary toprepare a counter in the receiver 2.

Accordingly, the present embodiment makes it possible to discriminatethe plurality of communication mode without using the counter. In thepresent embodiment, in the transmitter 1, the blanking controller 20 maycontrol, depending on the communication modes, a signal value of a datablanking signal and a signal value of a clock blanking signal to, forexample, values that enable discrimination of the communication modes asillustrated in FIGS. 9 and 10 to be described later. Moreover, in thereceiver 2, a clock state discrimination circuit 59 (FIG. 6) to bedescribed later may discriminate the communication modes with referenceto, for example, values illustrated in FIGS. 9 and 10 to be describedlater.

FIG. 9 illustrates a first example of respective signal waveforms to betransmitted on the clock lane CL and the data lane DL1 in thecommunication system according to the present embodiment. FIG. 9illustrates an example in which the communication mode in the blankingperiod is the first blanking mode (the LRTE mode).

FIG. 10 illustrates a second example of respective signal waveforms tobe transmitted on the clock lane CL and the data lane DL1 in thecommunication system according to the present embodiment. FIG. 10illustrates an example in which the communication mode in the blankingperiod is the second blanking mode (the ALP mode).

It is to be noted that a substantial data signal portion in FIGS. 9 and10 is referred to as “HST”. Periods before and after a substantial datasignal may include a SYNC (synchronization) period T_(HS-SYNC) and aTRAIL period T_(HS-TRAIL).

As illustrated in FIG. 6, the communication system according to thepresent embodiment may include the crystal oscillator (XTAL) 82, the PLLcircuit 81, the crystal oscillator (XTAL) 83, and a PPL circuit 84. Thecrystal oscillator (XTAL) 82 and the PLL circuit 81 each supply theclock signal to respective circuit portions in the transmitter 1. Thecrystal oscillator (XTAL) 83 and the PLL circuit 84 each supply theclock signal to respective circuit portions in the receiver 2.

(Specific Configuration Example of Transmitter 1)

On the clock lane CL, the transmitter 1 may include a CL-HS circuit 11that processes the HS differential signal. On the data lane DL1, thetransmitter 1 may include a DL-HS circuit 13 that processes the HSdifferential signal.

The CL-HS circuit 11 may be a differential clock signal transmittercircuit that outputs the clock signal and the HS differential signal asa clock blanking signal to the clock signal line 30. The DL-HS circuit13 may be a differential data signal transmitter circuit that outputsthe data signal and the HS differential signal as a data blanking signalto the data signal line 31.

The transmitter 1 according to the present embodiment may not includecircuits corresponding to the CL-LP circuit 112 and the DL-LP circuit114 that each process the LP signal in the foregoing comparativeexample.

The CL-HS circuit 11 may include a circuit substantially similar to theCL-HS circuit 111 in FIG. 3, as illustrated in FIG. 6. Morespecifically, the CL-HS circuit 11 may include the HS state machine (HSFSM) 51, the selector 52, the parallel-serial (PS) conversion circuit53, the clock frequency divider (DIV) 54, and the HS driver (HS DRV) 55.The selector 52 may selectively output the Toggle signal, the signalwith a value of 0 (ALL0), and the signal with a value of 1 (ALL1). TheToggle signal may be an 8-bit clock signal (1010_1010), for example. Inthe present embodiment, the clock lane control signal and the datatransmission request signal TxRequestHS may be inputted into the HSstate machine 51.

The DL-HS circuit 13 may include circuits substantially similar to theDL-HS circuit 113 in FIG. 3, as illustrated in FIG. 6. Morespecifically, the DL-HS circuit 13 may include the HS state machine (HSFSM) 71, the selector 72, the parallel-serial (PS) conversion circuit73, and the HS driver (HS DRV) 74. The HS state machine 71 may outputthe data transmission ready signal TxReadyHS. The selector 72 mayselectively output the transmission data TxDataHS, the synchronizationcode signal SYNC, the signal with a value of 0 (ALL0), and the signalwith a value of 1 (ALL1).

The blanking controller 20 may include the HS state machine 51 and theHS state machine 71, as illustrated in FIG. 6.

(Example of Mode Control Operation in Transmitter 1)

In a case in which communication by the first blanking mode in FIG. 9 isperformed, the blanking controller 20 may control the DL-HS circuit 13so as to output, for example, a data blanking signal with a value of 1,in place of the data signal from the DL-HS circuit 13, from the DL-HScircuit 13 to the data signal line 31 in synchronization with start timeof a blanking period of the data signal.

Moreover, in the case in which communication by the first blanking modeis performed, the blanking controller 20 may control the CL-HS circuit11 so as to output, for example, a differential blanking signal, inplace of the clock signal, from the CL-HS circuit 11 to the clock signalline 30 in synchronization with the start time of the blanking period ofthe data signal throughout a predetermined period or longer. In thedifferential blanking signal, a clock blanking signal with a value of 0may continue. The predetermined period herein is a period that is longerthan a clock cycle of the clock signal. The clock blanking signal is asignal continuously having a signal value of 0 throughout a periodlonger than the clock cycle of the clock signal, which makes it possibleto detect a signal change in the clock state discrimination circuit 59of the receiver 2, thereby detecting that the blanking period hasstarted.

Moreover, in the case in which communication by the first blanking modeis performed, the blanking controller 20 may control the CL-HS circuit11 so as to output the clock signal, in place of the clock blankingsignal, from the CL-HS circuit 11 to the clock signal line 30 insynchronization with end time of the blanking period of the data signalthroughout a predetermined period or longer. Outputting the clocksignal, in place of the clock blanking signal, throughout thepredetermined period or longer makes it possible to detect a signalchange in the clock state discrimination circuit 59 of the receiver 2,thereby detecting that the blanking period has ended and transfer of thedata signal is to start.

In contrast, in a case in which communication by the second blankingmode in FIG. 10 is performed, the blanking controller 20 may control theDL-HS circuit 13 so as to output a data blanking signal with a value of0, in place of the data signal, from the DL-HS circuit 13 to the datasignal line 31 in synchronization with the start time of the blankingperiod of the data signal.

Moreover, in the case in which communication by the second blanking modeis performed, the blanking controller 20 may control the CL-HS circuit11 so as to output, for example, a differential blanking signal, inplace of the clock signal, from the CL-HS circuit 11 to the clock signalline 30 in synchronization with the start time of the blanking period ofthe data signal throughout a predetermined period or longer. In thedifferential blanking signal, a clock blanking signal with a value of 0may continue. The predetermined period herein is a period longer thanthe clock cycle of the clock signal. The clock blanking signal is asignal continuously having a signal value of 0 throughout a periodlonger than the clock cycle of the clock signal, which makes it possibleto detect a signal change in the clock state discrimination circuit 59of the receiver 2, thereby detecting that the blanking period hasstarted.

Further, in the case in which communication by the second blanking modeis performed, the blanking controller 20 may control the CL-HS circuit11 so as to output, for example, a clock blanking signal with a value of1, in place of the clock blanking signal with a value of 0, from theCL-HS circuit 11 to the clock signal line 30 in synchronization with theend time of the blanking period of the data signal throughout apredetermined period or longer. Outputting the clock blanking signalwith a value of 1, in place of the clock blanking signal with a value of0, throughout the predetermined period or longer makes it possible todetect a signal change in the clock state discrimination circuit 59 ofthe receiver 2, thereby detecting that the blanking period has ended andtransfer of the data signal is to start.

As with the examples illustrated in FIGS. 9 and 10, the value of thedata blanking signal at the start of the blanking period of the datasignal is different between the first blanking mode and the secondblanking mode, which makes it possible to discriminate the communicationmodes in the clock state discrimination circuit 59 of the receiver 2.

It is to be noted that the values of the clock blanking signal and thedata blanking signal illustrated in FIGS. 9 and 10 are merely examples,and different values from the values in the examples in FIGS. 9 and 10may be used.

FIG. 11 illustrates an example of a value of a differential signal. Theclock blanking signal with a value of 0 and the data blanking signalwith a value of 0 may be differential signals with a differential of 0(Differential-0). Moreover, the clock blanking signal with a value of 1and the data blanking signal with a value of 1 may be differentialsignals with a differential of 1 (Differential-1). More specifically, asillustrated in FIG. 11, the differential signal with a value of 0 may bea differential signal in which a voltage level of a positive signal lineDp and a voltage level of a negative signal line Dn on a transmissionline of the differential signal are low and high, respectively.Moreover, the differential signal with a value of 1 may be adifferential signal in which the voltage level of the positive signalline Dp and the voltage level of the negative signal line Dn on thetransmission line of the differential signal are high and low,respectively.

(Specific Configuration Example of Receiver 2)

On the clock lane CL, the receiver 2 may include a CL-HS circuit 21 thatprocesses the HS differential signal. On the data lane DL1, the receiver2 may include a DL-HS circuit 23 that processes the HS differentialsignal.

The DL-HS circuit 23 may be a differential data signal receiver circuitthat receives the data signal and the HS differential signal as a datablanking signal through the data signal line 31. The CL-HS circuit 21may be a differential clock signal receiver circuit that receives theclock signal and the HS differential signal as a clock blanking signalthrough the clock signal line 30.

The receiver 2 according to the present embodiment may not includecircuits corresponding to the CL-LP circuit 122 and the DL-LP circuit124 that each process the LP signal in the foregoing comparativeexample.

The DL-HS circuit 23 may include a circuit substantially similar to theDL-HS circuit 123 in FIG. 3, as illustrated in FIG. 6. Morespecifically, the DL-HS circuit 23 may include the termination circuit(TERM) 75 serving as a data signal termination circuit coupled to thedata signal line 31, the HS receiver (HS RCV) 76, the clock frequencydivider (DIV) 77, and the word alignment correction circuit (ALN) 78.The termination circuit 75 may include a terminator. The word alignmentcorrection circuit (ALN) 78 may output the reception synchronizationsignal RxSyncHS, the reception valid signal RxValidHS, and the receptiondata RxDataHS.

The CL-HS circuit 21 may include a circuit substantially similar to theCL-HS circuit 121 in FIG. 3, as illustrated in FIG. 6. Morespecifically, the CL-HS circuit 21 may include the termination circuit(TERM) 56 serving as a clock signal termination circuit coupled to theclock signal line 30, the HS receiver (HS RCV) 57, and the clockfrequency divider (DIV) 58. The termination circuit 56 may include aterminator.

The CL-HS circuit 21 may further include the clock (CL) statediscrimination circuit 59. The clock signal and the clock blankingsignal from the CL-HS circuit 11 of the transmitter 1 may be inputted tothe clock state discrimination circuit 59 through the HS receiver 57.Moreover, the data blanking signal from the DL-HS circuit 13 of thetransmitter 1 may be inputted to the clock state discrimination circuit59 through the HS receiver 76.

(Example of Mode Discrimination in Receiver 2)

The clock state discrimination circuit 59 may discriminate the blankingmodes with reference to, for example, the value of the data blankingsignal at the start of the blanking period of the data signal. Forexample, in a case in which the value of the data blanking signal is 1as with the example in FIG. 9, the clock state discrimination circuit 59may discriminate that the blanking mode is the first blanking mode.Moreover, for example, in a case in which the value of the data blankingsignal is 0 as with the example in FIG. 10, the clock statediscrimination circuit 59 may discriminate that the blanking mode is thesecond blanking mode.

(Examples of Termination Control and Word Alignment Control in Receiver2)

In the case of the second blanking mode as with the example in FIG. 10,the receiver 2 may perform a termination control process. The clockstate discrimination circuit 59 may function as a termination controlcircuit. The clock state discrimination circuit 59 may perform controlto cause the terminator of the data signal termination circuit (thetermination circuit 75) and the terminator of the clock signaltermination circuit (the termination circuit 56) to be turned off on thebasis of, for example, the clock blanking signal with a value of 0.Moreover, the clock state discrimination circuit 59 may perform controlto cause the terminator of the termination circuit 75 and the terminatorof the termination circuit 56 to be turned on, on the basis of the clockblanking signal with a value of 1 that is outputted in synchronizationwith the end time of the blanking period of the data signal.

It is to be noted that voltage amplitudes of the signals in the blankingperiods on the clock lane CL and the data lane DL1 are changed when theterminators are turned on or off, as illustrated in FIG. 10. Moreover,turning off the terminator in the blanking period makes it possible toreduce values of currents flowing through the clock signal line 30 andthe data signal line 31.

Moreover, the clock state discrimination circuit 59 may have a functionof outputting the reception active signal RxActiveHS and performing wordalignment control on the word alignment correction circuit 78. The clockstate discrimination circuit 59 properly detects that the blankingperiod is ended and transfer of the data signal starts, which makes itpossible for the word alignment correction circuit 78 to perform wordalignment control properly.

Effects

As described above, according to the present embodiment, thedifferential blanking signal in which the predetermined value continuesthroughout the predetermined period or longer is outputted as the clockblanking signal, in place of the clock signal, to the clock signal line30 in synchronization with the start time of the blanking period of thedata signal, which makes it possible to reduce power consumption duringdata transmission. Moreover, according to the present embodiment, ascompared with the communication system according to the foregoingcomparative example, the circuit that processes the LP signal isunnecessary, which makes it possible to reduce a circuit size.

Further, according to the present embodiment, the signal value of thedata blanking signal is controlled to a value that enablesdiscrimination of the blanking modes in the transmitter 1, and theblanking modes are discriminated on the basis of the signal value of thedata blanking signal in the receiver 2. This makes it possible to easilyperform discrimination of a plurality of blanking modes without using acounter for discrimination of the blanking modes in the receiver 2.

Note that the effects described in the present specification areillustrative and nonlimiting. Effects achieved by the technology may beeffects other than those described in the present specification. Thesame applies to effects of other embodiments.

2. SECOND EMBODIMENT

Next, description is given of a second embodiment of the presentdisclosure. Hereinafter, description of configurations and workingssubstantially similar to those in the foregoing comparative example andthe foregoing first embodiment is omitted.

FIG. 12 illustrates an outline of a communication system according to asecond embodiment of the present disclosure. The communication systemaccording to the present embodiment includes a transmitter 1B (atransmission device) corresponding to the transmitter TX in FIG. 1 and areceiver 2B (a reception device) corresponding to the receiver RX inFIG. 1.

In the communication system according to the foregoing first embodiment,all signals to be transmitted on the clock lane CL and the data lane DL1including the blanking period are HS differential signals only. Incontrast, the communication system according to the present embodimentmay include a switching circuit that makes it possible to performcommunication using the LP signal. The switching circuit makes itpossible to perform switching between a mode in which communicationusing the HS differential signal without using the LP signal isperformed and a mode in which communication using both the LP signal andthe HS differential signal is performed.

In the communication system according to the present embodiment, thetransmitter 1B may include the blanking controller 20 that achieve afunction substantially similar to that of the communication systemaccording to the foregoing first embodiment.

Moreover, the transmitter 1B may include the CL-HS circuit 11 thatprocesses the HS differential signal, a CL-LP circuit 12 that processesthe LP signal, a selector switch 15, and a selector 17 on the clock laneCL.

The CL-LP circuit 12 may be a first single-ended signal transmittercircuit that outputs a first signal-ended signal as the LP signal. TheCL-LP circuit 12 may have a function substantially similar to that ofthe CL-LP circuit 112 in FIG. 2. The selector switch 15 may be a firsttransmission switching circuit that switches a signal output path tocause one of the CL-HS circuit 11 and the CL-LP circuit 12 to output asignal to the clock signal line 30. The selector 17 may be a circuitthat causes a control signal from the blanking controller 20 to beinputted to the CL-HS circuit 11 in a mode in which communication usingonly the HS differential signal without using the LP signal isperformed, and prevents the control signal from the blanking controller20 from being inputted to the CL-HS circuit 11 in a mode in whichcommunication using both the LP signal and the HS differential signal isperformed.

Moreover, the transmitter 1B may include the DL-HS circuit 13 thatprocesses the HS differential signal, the DL-LP circuit 14 thatprocesses the LP signal, a selector switch 16, and a selector 18 on thedata lane DL1.

The DL-LP circuit 14 may be a second single-ended signal transmittercircuit that outputs a second single-ended signal as the LP signal. TheDL-LP circuit 14 may have a function substantially similar to that ofthe DL-LP circuit 114 in FIG. 2. The selector switch 16 may be a secondtransmission switching circuit that switches a signal output path tocause one of the DL-HS circuit 13 and the DL-LP circuit 14 to output asignal to the data signal line 31. The selector 18 may be a circuit thatcauses a control signal from the blanking controller 20 to be inputtedto the DL-HS circuit 13 in the mode in which communication using onlythe HS differential signal without using the LP signal is performed, andprevents the control signal from the blanking controller 20 from beinginputted to the DL-HS circuit 13 in the mode in which communicationusing both the LP signal and the HS differential signal is performed.

The receiver 2B may include the CL-HS circuit 21 that processes the HSdifferential signal, a CL-LP circuit 22 that processes the LP signal, aselector 25, a selector 27, and a selector 28. The CL-LP circuit 22 maybe a first single-ended signal receiver circuit that receives the firstsingle-ended signal as the LP signal through the clock signal line 30.The CL-LP circuit 22 may have a function substantially similar to thatof the CL-LP circuit 122 in FIG. 2.

The selector 25 may be a first reception switching circuit that performsswitching whether to receive the first single-ended signal as the LPsignal. The selector 25 may be a circuit that prevents a signal receivedthrough the clock signal line 30 from being inputted to the CL-LPcircuit 22 in the mode in which communication using only the HSdifferential signal without using the LP signal is performed, and causesthe signal received through the clock signal line 30 to be inputted tothe CL-LP circuit 22 in the mode in which communication using both theLP signal and the HS differential signal is performed. The selector 27may be a circuit that inputs a termination control signal from the CL-HScircuit 21 to the DL-HS circuit 23 in the mode in which communicationusing only the HS differential signal without using the LP signal isperformed, and prevents the termination control signal from the CL-HScircuit 21 from being inputted to the DL-HS circuit 23 in the mode inwhich communication using both the LP signal and the HS differentialsignal is performed. The selector 28 may be a circuit that causes a wordalignment control signal from the CL-HS circuit 21 to be inputted to theDL-HS circuit 23 in the mode in which communication using only the HSdifferential signal without using the LP signal is performed, andprevents the word alignment control signal from the CL-HS circuit 21from being inputted to the DL-HS circuit 23 in the mode in whichcommunication using both the LP signal and the HS differential signal isperformed.

Moreover, the receiver 2B may include the DL-HS circuit 23 thatprocesses the HS differential signal, a DL-LP circuit 24 that processesthe LP signal, and a selector 26 on the data lane DL1. The DL-LP circuit24 may be a second single-ended signal receiver circuit that receivesthe second single-ended signal as an LP signal through the data signalline 31.

The selector 26 may be a second reception switching circuit thatperforms whether to receive the second single-ended signal as the LPsignal. The selector 26 may be a circuit that prevents a signal receivedthrough the data signal line 31 from being inputted to the DL-LP circuit24 in the mode in which communication using only the HS differentialsignal without using the LP signal is performed, and causes the signalreceived through the data signal line 31 to be inputted to the DL-LPcircuit 24 in the mode in which communication using both the LP signaland the HS differential signal is performed.

FIG. 13 illustrates a specific application example of the communicationsystem according to the present embodiment.

For example, the communication system according to the presentembodiment is applicable to data transmission from an image sensor IS toan application processor AP, as illustrated in FIG. 13. The transmitter1B may be provided in the image sensor IS. The receiver 2B may beprovided in the application processor AP. The image sensor IS and theapplication processor AP may be coupled to each other through the clocksignal line 30 and the data signal line 31. Signals may be transmittedthrough the clock signal line 30 and the data signal line 31 in onedirection.

Moreover, the image sensor IS and the application processor AP may becoupled to each other through a bidirectional control bus 35. Thecontrol bus 35 may use an I²C (Inter-Integrated Circuit) interface or anI³C interface that is an extension of the I²C interface.

FIG. 14 illustrates an example of a data transmission process in adevice including the image sensor IS and the application processor APillustrated in FIG. 13.

The device including the image sensor IS and the application processorAP may be powered on (step S101). The application processor AP may reada register setting of the image sensor IS with use of the control bus 35(step S102). Thus, the application processor AP may determine whetherthe image sensor IS corresponds to communication without the LP signal(step S103). In other words, the application processor AP may determinewhether the image sensor IS corresponds to the mode in whichcommunication using only the HS differential signal without using the LPsignal is performed or the mode in which communication using both the LPsignal and the HS differential signal is performed.

In a case in which the application processor AP determines that theimage sensor IS does not correspond to communication without the LPsignal (step S103; N), the application processor AP may determine thatthe image sensor IS is in the mode in which communication using both theLP signal and the HS differential signal is performed, and may output atransmission start command signal to the image sensor IS with use of thecontrol bus 35 (step S109). Next, the image sensor IS may starttransmission of the data signal in response to the transmission startcommand signal (step S110).

In contrast, in a case in which the application processor AP determinesthat the image sensor IS corresponds to communication without the LPsignal (step S103; Y), the application processor AP may transmit asetting for validating communication without the LP signal to the imagesensor IS (step S104).

Next, the application processor AP may determine whether the imagesensor IS corresponds to communication by the first blanking mode (theLRTE mode) with reference to the register setting of the image sensor IS(step S105). In a case in which the application processor AP determinesthat the image sensor IS does not correspond to communication by thefirst blanking mode (step S105; N), the flow of the data transmissionprocess proceeds to a process in step S107 to be described later. In acase in which the application processor AP determines that the imagesensor IS corresponds to communication by the first blanking mode (stepS105; Y), the application processor AP may transmit a setting forvalidating communication by the first blanking mode to the image sensorIS with use of the control bus 35 (step S106).

Next, the application processor AP may determine whether the imagesensor IS corresponds to communication by the second blanking mode (theALP mode) with reference to the register setting of the image sensor IS(step S107). In a case in which the application processor AP determinesthat the image sensor IS does not correspond to communication by thesecond blanking mode (step S107; N), the application processor AP mayoutput a transmission start command signal to the image sensor IS withuse of the control bus 35 (step S109). Next, the image sensor IS maystart transmission of the data signal in response to the transmissionstart command signal (step S110).

In contrast, in a case in which the application processor AP determinesthat the image sensor corresponds to communication by the secondblanking mode (step S107: Y), the application processor AP may transmita setting for validating communication by the second blanking mode tothe image sensor IS with use of the control bus 35 (step S108). Next,the application processor AP may output the transmission start commandsignal to the image sensor IS with use of the control bus 35 (stepS109). Next, the image sensor IS may start transmission of the datasignal in response to the transmission start command signal (step S110).

3. THIRD EMBODIMENT

Next, description is given of a third embodiment of the presentdisclosure. Hereinafter, description of configurations and workingssubstantially similar to those in the foregoing comparative example, theforegoing first embodiment, and the foregoing second embodiment isomitted.

In the foregoing first and second embodiments, an example in whichdiscrimination of the blanking modes is performed as discrimination ofthe communication modes is described; however, it is possible todiscriminate communication modes (data transmission modes) of a datasignal by a similar discrimination technique.

FIG. 15 illustrates an example of data transmission modes to bediscriminated in the present embodiment. In the present embodiment, asthe data transmission modes, for example, a first data transmission mode(a high-speed transmission mode) in which transmission speed isrelatively high and a second data transmission mode (a low-speedtransmission mode) in which the transmission speed is relatively low maybe discriminated. The high-speed transmission mode and the low-speedtransmission mode may be both modes in which a differential signal istransmitted, and may have different transmission speed, for example, bychanging a voltage amplitude.

It is to be noted that a basic configuration of the communication systemin the present embodiment may be substantially similar to theconfiguration in FIGS. 5 and 6. In the transmitter 1, the blankingcontroller 20 may control, depending on the communication modes, thesignal value of the data blanking signal and the signal value of theclock blanking signal to, for example, values that enable discriminationof the communication modes as illustrated in FIGS. 17, 19, and 21 to bedescribed later. Moreover, in the receiver 2, the clock statediscrimination circuit 59 may discriminate the communication modes withreference to, for example, values illustrated in FIGS. 17, 19 and 21 tobe described later.

(First Example of Method of Discriminating Data Transmission Modes)

FIG. 16 illustrates a first example of respective signal waveforms to betransmitted on the clock lane CL and the data lane DL1 in thecommunication system according to the present embodiment. FIG. 16illustrates an example in which the communication mode in the blankingperiod is the first blanking mode (the LRTE mode), as with the examplein FIG. 9. FIG. 17 illustrates an example of a method of discriminatingthe communication modes of the data signal in a case in which thecommunication mode in the blanking period is the first blanking mode.

The blanking controller 20 may control the DL-HS circuit 13 so as tooutput, for example, a data blanking signal with a value D_(m)0, inplace of the data signal, from the DL-HS circuit 13 to the data signalline 31 in synchronization with the start time of the blanking period ofthe data signal.

Moreover, the blanking controller 20 may control the CL-HS circuit 1 soas to output, in place of the clock signal, a differential blankingsignal from the CL-HS circuit 11 to the clock signal line 30 insynchronization with the start time of the blanking period of the datasignal throughout a predetermined period or longer. In the differentialblanking signal, a clock blanking signal with a value C_(nt)0 maycontinue. The predetermined period herein is a period that is longerthan the clock cycle of the clock signal. The clock blanking signal is asignal continuously having the signal value C_(nt)0 throughout a periodlonger than the clock cycle of the clock signal, which makes it possibleto detect a signal change in the clock state discrimination circuit 59of the receiver 2, thereby detecting that the blanking period hasstarted.

Further, the blanking controller 20 may control the CL-HS circuit 11 soas to output the clock signal, in place of the clock blanking signal,from the CL-HS circuit 11 to the clock signal line 30 in synchronizationwith the end time of the blanking period of the data signal throughout apredetermined period or longer. Outputting the clock signal, in place ofthe clock blanking signal, throughout the predetermined period or longermakes it possible to detect a signal change in the clock statediscrimination circuit 59 of the receiver 2, thereby detecting that theblanking period has ended and transfer of the data signal is to start.

In the receiver 2, the clock state discrimination circuit 59 maydiscriminate the communication modes with reference to the values asillustrated in FIG. 17, for example.

The clock state discrimination circuit 59 may discriminate that thecommunication mode is the high-speed transmission mode in a case of(C_(nt)0=0, D_(nt)0=0) and is the low-speed transmission mode in a caseof (C_(nt)0=1, D_(nt)0=1), for example. Moreover, the clock statediscrimination circuit 59 may discriminate that the communication modein the blanking period is the first blanking mode (the LRTE mode) in acase of (C_(nt)0=0, D_(nt)0=1), for example. It is to be noted that(C_(nt)0=1, D_(nt)0=0) may be reserved value (“Reserved”) that is usablefor discrimination of any other communication mode in future, forexample.

It is to be noted that combinations of the values illustrated in FIG. 17and the communication modes are merely examples, and a combination otherthan the combinations in FIG. 17 may be adopted. Moreover,discrimination of three or more kinds of data transmission modes may beperformed.

(Second Example of Method of Discriminating Data Transmission Modes)

FIG. 18 illustrates a second example of respective signal waveforms tobe transmitted on the clock lane CL and the data lane DL1 in thecommunication system according to the present embodiment. FIG. 18illustrates an example in which the communication mode in the blankingperiod is the second blanking mode (the ALP mode) as with the example inFIG. 10. FIG. 19 illustrates an example of a method of discriminatingthe communication modes of the data signal in a case in which thecommunication mode in the blanking period is the second blanking mode.

The blanking controller 20 may control the DL-HS circuit 13 so as tooutput, for example, a data blanking signal with a value D0, in place ofthe data signal, from the DL-HS circuit 13 to the data signal line 31 insynchronization with the start time of the blanking period of the datasignal. Moreover, the blanking controller 20 may control the DL-HScircuit 13 so as to output, in place of the data blanking signal withthe value D0, a data blanking signal with a value D1 from the DL-HScircuit 13 to the data signal line 31 in synchronization with the endtime of the blanking period.

Further, the blanking controller 20 may control the CL-HS circuit 11 soas to output, in place of the clock signal, a differential blankingsignal from the CL-HS circuit 11 to the clock signal line 30 insynchronization with the start time of the blanking period of the datasignal throughout a predetermined period or longer. In the differentialblanking signal, a clock blanking signal with a value C0 may continue.The predetermined period herein is a period that is longer than theclock cycle of the clock signal. The clock blanking signal is a signalcontinuously having the signal value C0 throughout a period longer thanthe clock cycle of the clock signal, which makes it possible to detect asignal change in the clock state discrimination circuit 59 of thereceiver 2, thereby detecting that the blanking period has started.

Moreover, the blanking controller 20 may control the CL-HS circuit 11 soas to output the clock blanking signal with a value C1, in place of theclock blanking signal with the value C0, from the CL-HS circuit 11 tothe clock signal line 30 in synchronization with the end time of theblanking period of the data signal throughout a predetermined period orlonger. Outputting the clock blanking signal with the value C1, in placeof the clock blanking signal with the value C0, throughout thepredetermined period or longer makes it possible to detect a signalchange in the clock state discrimination circuit 59 of the receiver 2,thereby detecting that the blanking period has ended and transfer of thedata signal is to start.

In the receiver 2, the clock state discrimination circuit 59 maydiscriminate the communication modes with reference to the values asillustrated in FIG. 19, for example.

The clock state discrimination circuit 59 may discriminate that thecommunication mode is the high-speed transmission mode in a case of(C0=0, C1=1) and (D0=0, D1=0), for example. Moreover, the clock statediscrimination circuit 59 may discriminate that the communication modeis the low-speed transmission mode in a case of (C0=0, C1=1) and (D0=0,D1=1), for example. It is to be noted that other values may be reservedvalues (“Reserved”) that are usable for discrimination of othercommunication modes in future, for example. However, in order to performtermination control, it is necessary to change at least one of the value(C0, C1) of the clock blanking signal and the value (D0, D1) of the datablanking signal within the blanking period. Accordingly, in a case inwhich the termination control is performed, cases of (C0=0, C1=0) and(D0=0, D1=0), (C0=0, C1=0) and (D0=1, D1=1), (C0=1, C1=1) and (D0=0,D1=0), (C0=−1, C1=1) and (D0=1, D1=1) are not used for discrimination ofthe communication modes.

It is to be noted that combinations of the values illustrated in FIG. 19and the communication modes are merely examples, and a combination otherthan the combinations in FIG. 19 may be adopted. Moreover,discrimination of three or more kinds of data transmission modes may beperformed.

(Third Example of Method of Discriminating Data Transmission Modes)

FIG. 20 illustrates a third example of respective signal waveforms to betransmitted on the clock lane CL and the data lane DL1 in thecommunication system according to the present embodiment. FIG. 21illustrates an example of a method of discriminating the communicationmodes in the third example illustrated in FIG. 20.

FIG. 20 illustrates an example in which transition of the communicationmodes takes place in order of the high-speed transmission mode, the LRTEmode, the low-speed transmission mode, and the high-speed transmissionmode.

In the receiver 2, as with the second example mentioned above, the clockstate discrimination circuit 59 may discriminate the communication modewith reference to the value (C0, C1) on the clock lane CL and the value(D0, D1) on the data lane DL1 as illustrated in FIG. 21, for example. Itis to be noted that FIG. 21 illustrates an example of an on-off state ofthe terminator during mode transition.

The clock state discrimination circuit 59 may discriminate that thecommunication mode is changed to the high-speed transmission mode in acase of (C0=0, C1=1) and (D0=0, D1=0), for example. Moreover, the clockstate discrimination circuit 59 may discriminate that the communicationmode is changed to the LRTE mode in a case of (C0=0, C1=0) and (D0=1,D1=1), for example. Further, the clock state discrimination circuit 59may discriminate that the communication mode is changed to the low-speedtransmission mode in a case of (C0=0. C1=1) and (D0=0, D1=1), forexample. It is to be noted that other values may be reserved values(“Reserved”) that are usable for discrimination of other communicationmodes in future, for example.

It is to be noted that combinations of the values illustrated in FIG. 21and the communication modes are merely examples, and combinations otherthan the combinations in FIG. 21 may be adopted.

4. APPLICATION EXAMPLES

Next, description is given of application examples of the communicationsystems described in the foregoing respective embodiments.

4.1 First Application Example

FIG. 22 illustrates an appearance of a smartphone 300 (a multifunctionalmobile phone) to which any of the communication systems according to theforegoing respective embodiments is applied. Various devices are mountedin the smartphone 300. Any of the communication systems according to theforegoing respective embodiments is applied to a communication systemthat exchanges data between these devices.

FIG. 23 illustrates a configuration example of an application processor310 used in the smartphone 300. The application processor 310 mayinclude a central processing unit (CPU) 311, a memory controller 312, apower source controller 313, an external interface 314, a graphicsprocessing unit (GPU) 315, a media processor 316, a display controller317, and a mobile industry processor interface (MIPI) interface 318. Inthis example, the CPU 311, the memory controller 312, the power sourcecontroller 313, the external interface 314, the GPU 315, the mediaprocessor 316, and the display controller 317 may be coupled to a systembus 319 to allow for data exchange through the system bus 319.

The CPU 311 may be adapted to process various pieces of informationhandled in the smartphone 300 in accordance with a program. The memorycontroller 312 may be adapted to control the memory 501 used when theCPU 311 performs information processing. The power source controller 313may be adapted to control a power source of the smartphone 300.

The external interface 314 may be an interface for communication withexternal devices. In this example, the external interface 314 may becoupled to a wireless communication section 502 and an image sensor 410.The wireless communication section 502 may be adapted to carry outwireless communication with mobile phone base stations. The wirelesscommunication section 502 may include, for example, a baseband section,a radio frequency (RF) front end section, and other components. Theimage sensor 410 may be adapted to acquire an image, and may include,for example, a CMOS sensor.

The GPU 315 may be adapted to perform image processing. The mediaprocessor 316 may be adapted to process information such as voice,characters, and graphics. The display controller 317 may be adapted tocontrol the display 504 through the MIPI interface 318.

The MIPI interface 318 may be adapted to transmit an image signal to thedisplay 504. As the image signal, for example, a YUV-format signal, anRGB-format signal, or any other format signal may be used. For example,any of the communication systems according to the foregoing respectiveembodiments may be applied to a communication system between the MIPIinterface 318 and the display 504.

FIG. 24 illustrates a configuration example of the image sensor 410. Theimage sensor 410 may include a sensor 411, an image signal processor(ISP) 412, a joint photographic experts group (JPEG) encoder 413, a CPU414, a random access memory (RAM) 415, a read only memory (ROM) 416, apower source controller 417, an inter-integrated circuit (I²C) interface418, and an MIPI interface 419. In this example, these blocks arecoupled to a system bus 420 to allow for data exchange through thesystem bus 420.

The sensor 411 may be adapted to acquire an image, and may be configuredof, for example, a CMOS sensor. The ISP 412 may be adapted to performpredetermined processing on the image acquired by the sensor 411. TheJPEG encoder 413 may be adapted to encode the image processed by the ISP412 to generate a JPEG-format image. The CPU 414 may be adapted tocontrol respective blocks of the image sensor 410 in accordance with aprogram. The RAM 415 may be a memory used when the CPU 414 performsinformation processing. The ROM 416 may be adapted to store a program tobe executed in the CPU 414. The power source controller 417 may beadapted to control a power source of the image sensor 410. The I²Cinterface 418 may be adapted to receive a control signal from theapplication processor 310. Although not illustrated, the image sensor410 may be adapted to also receive a clock signal from the applicationprocessor 310, in addition to the control signal. More specifically, theimage sensor 410 may be configured to be operable on the basis of clocksignals of various frequencies.

The MIPI interface 419 may be adapted to transmit an image signal to theapplication processor 310. As the image signal, for example, aYUV-format signal, an RGB-format signal, or any other format signal maybe used. For example, any of the communication systems according to theforegoing respective embodiments may be applied to a communicationsystem between the MIPI interface 419 and the application processor 310.

4.2 Second Application Example

FIG. 25 and FIG. 26 each illustrate a configuration example of avehicle-mounted camera as an application example to an imaging device.FIG. 25 illustrates an installation example of the vehicle-mountedcamera, and FIG. 26 illustrates an internal configuration example of thevehicle-mounted camera.

For example, vehicle-mounted cameras 401, 402, 403, and 404 may berespectively mounted on the front, left, right, and rear of a vehicle301, as illustrated in FIG. 25. The vehicle-mounted cameras 401 to 404may be coupled to an electrical control unit (ECU) 302 through anin-vehicle network.

An image capturing angle of the vehicle-mounted camera 401 mounted onthe front of the vehicle 301 may be within a range indicated by “a” inFIG. 25, for example. An image capturing angle of the vehicle-mountedcamera 402 may be within a range indicated by “b” in FIG. 25, forexample. An image capturing angle of the vehicle-mounted camera 403 maybe within a range indicated by “c” in FIG. 25, for example. An imagecapturing angle of the vehicle-mounted camera 404 may be within a rangeindicated by “d” in FIG. 25, for example. Each of the vehicle-mountedcameras 401 to 404 may output a captured image to the ECU 302. Thismakes it possible to capture a 360-degree (omnidirectional) image on thefront, right, left, and rear of the vehicle 301 in the ECU 302.

For example, each of the vehicle-mounted cameras 401 to 404 may includean image sensor 431, a digital signal processing (DSP) circuit 432, aselector 433, and a serializer-deserializer (SerDes) circuit 434, asillustrated in FIG. 26.

The DSP circuit 432 may be adapted to perform various kinds of imagesignal processing on an imaging signal outputted from the image sensor431. The SerDes circuit 434 may be adapted to perform serial-parallelconversion of a signal, and may be configured of, for example, avehicle-mounted interface chip such as DPD-Link Ill.

The selector 433 may be adapted to select whether to output the imagingsignal outputted from the image sensor 431 through the DSP circuit 432or not through the DSP circuit 432.

Any of the communication systems according to the foregoing respectiveembodiments may be applied to, for example, a connection interface 441between the image sensor 431 and the DSP circuit 432. Moreover, any ofthe communication systems according to the foregoing respectiveembodiments may be applied to, for example, a connection interface 442between the image sensor 431 and the selector 433.

5. OTHER EMBODIMENTS

The technology achieved by the present disclosure is not limited to thatdescribed in the foregoing respective embodiments, and may be modifiedin a variety of ways.

The present technology may have the following configurations.

(1)

A reception device, including:

a data signal receiver circuit that receives a data signal through adata signal line, and receives a data blanking signal through the datasignal line in a blanking period of the data signal;

a clock signal receiver circuit that receives a clock signal and a clockblanking signal through a clock signal line, the clock blanking signaloutputted in synchronization with the blanking period of the datasignal; and

a discrimination circuit that discriminates communication modes on abasis of one or both of a signal value of the data blanking signal and asignal value of the clock blanking signal.

(2)

The reception device according to (1), wherein the discriminationcircuit discriminates at least communication modes in the blankingperiod.

(3)

The reception device according to (2), wherein the discriminationcircuit discriminates, as the communication modes in the blankingperiod, a first blanking mode and a second blanking mode in which atransmission period is longer than a transmission period in the firstblanking mode.

(4)

The reception device according to any one of (1) to (3), wherein thediscrimination circuit discriminates at least communication modes of thedata signal.

(5)

The reception device according to (4), wherein the discriminationcircuit discriminates, as the communication modes of the data signal, afirst data transmission mode and a second data transmission mode inwhich transmission speed is lower than transmission speed in the firstdata transmission mode.

(6)

The reception device according to any one of (1) to (5), wherein

the data signal receiver circuit is a differential data signal receivercircuit that receives the data signal, and a differential signal as thedata blanking signal through the data signal line, and

the clock signal receiver circuit is a differential clock signalreceiver circuit that receives the clock signal, and a differentialsignal as the clock blanking signal through the clock signal line.

(7)

A transmission device, including:

a data signal transmitter circuit that outputs a data signal to a datasignal line, and outputs a data blanking signal through the data signalline in a blanking period of the data signal;

a clock signal transmitter circuit that outputs a clock signal to aclock signal line, and outputs a clock blanking signal, in place of theclock signal, in synchronization with the blanking period of the datasignal; and

a blanking controller that controls one or both of a signal value of thedata blanking signal and a signal value of the clock blanking signal toa value that enables discrimination of communication modes.

(8)

The transmission device according to (7), wherein the blankingcontroller controls the signal value to a value that enablesdiscrimination of at least communication modes in the blanking period.

(9)

The transmission device according to (8), wherein the blankingcontroller controls the signal value to a value that enablesdiscrimination of a first blanking mode and a second blanking mode asthe communication modes in the blanking period, the second blanking modein which a transmission period is longer than a transmission period inthe first blanking mode.

(10)

The transmission device according to any one of (7) to (9), wherein theblanking controller controls the signal value to a value that enablesdiscrimination of at least communication modes of the data signal.

(11)

The transmission device according to (10), wherein the blankingcontroller controls the signal value to a value that enablesdiscrimination of a first data transmission mode and a second datatransmission mode as the communication modes of the data signal, thesecond data transmission mode in which transmission speed is lower thantransmission speed in the first data transmission mode.

(12)

The transmission device according to any one of (7) to (11), wherein thedata signal transmitter circuit is a differential data signaltransmitter circuit that outputs the data signal, and a differentialsignal as the data blanking signal through the data signal line, and

the clock signal transmitter circuit is a differential clock signaltransmitter circuit that outputs the clock signal, and a differentialsignal as the clock blanking signal through the clock signal line.

(13)

A communication system, including:

a transmission device; and

a reception device,

the transmission device including:

a data signal transmitter circuit that outputs a data signal to a datasignal line, and outputs a data blanking signal through the data signalline in a blanking period of the data signal,

a clock signal transmitter circuit that outputs a clock signal to aclock signal line, and outputs a clock blanking signal, in place of theclock signal, in synchronization with the blanking period of the datasignal, and

a blanking controller that controls one or both of a signal value of thedata blanking signal and a signal value of the clock blanking signal toa value that enables discrimination of communication modes, and

the reception device including:

a data signal receiver circuit that receives the data signal and thedata blanking signal through the data signal line,

a clock signal receiver circuit that receives the clock signal and theclock blanking signal through the clock signal line, and

a discrimination circuit that discriminates the communication modes on abasis of one or both of the signal value of the data blanking signal andthe signal value of the clock blanking signal.

(14)

A signal reception method, including:

receiving a data signal through a data signal line, and receiving a datablanking signal through the data signal line in a blanking period of thedata signal;

receiving a clock signal and a clock blanking signal through a clocksignal line, the clock blanking signal outputted in synchronization withthe blanking period of the data signal; and

discriminating communication modes on a basis of one or both of a signalvalue of the data blanking signal and a signal value of the clockblanking signal.

(15)

A signal transmission method, including:

outputting a data signal to a data signal line, and outputting a datablanking signal through the data signal line in a blanking period of thedata signal;

outputting a clock signal to a clock signal line, and outputting a clockblanking signal, in place of the clock signal, in synchronization withthe blanking period of the data signal; and

controlling one or both of a signal value of the data blanking signaland a signal value of the clock blanking signal to a value that enablesdiscrimination of communication modes.

(16)

A communication method, including:

outputting a data signal to a data signal line, and outputting a datablanking signal through the data signal line in a blanking period of thedata signal;

outputting a clock signal to a clock signal line, and outputting a clockblanking signal, in place of the clock signal, in synchronization withthe blanking period of the data signal;

controlling one or both of a signal value of the data blanking signaland a signal value of the clock blanking signal to a value that enablesdiscrimination of a communication mode;

receiving the data signal and the data blanking signal through the datasignal line;

receiving the clock signal and the clock blanking signal through theclock signal line; and

discriminating the communication modes on a basis of one or both of thesignal value of the data blanking signal and the signal value of theclock blanking signal.

It should be understood by those skilled in the art that variousmodifications, combinations, sub-combinations and alterations may occurdepending on design requirements and other factors insofar as they arewithin the scope of the appended claims or the equivalents thereof.

REFERENCE SIGNS LIST

-   1, 1B transmitter (transmission device)-   2, 2B receiver (reception device)-   11 CL-HS circuit (differential clock signal transmitter circuit)-   12 CL-LP circuit (first single-ended signal transmitter circuit)-   13 DL-HS circuit (differential data signal transmitter circuit)-   14 DL-LP circuit (second single-ended signal transmitter circuit)-   15 selector switch (first transmission switching circuit)-   16 selector switch (second transmission switching circuit)-   17 selector-   18 selector-   20 blanking controller-   21 CL-HS circuit (differential clock signal receiver circuit)-   22 CL-LP circuit (first single-ended signal receiver circuit)-   23 DL-HS circuit (differential data signal receiver circuit)-   24 DL-LP circuit (second single-ended signal receiver circuit)-   25 selector (first reception switching circuit)-   26 selector (second reception switching circuit)-   27 selector-   28 selector-   30 clock signal line-   31 data signal line-   32 data signal line-   33 data signal line-   34 data signal line-   35 control bus-   41 LP state machine (LP FSM)-   42 LP encoder (LP ENC)-   43 LP driver (LP DRV)-   44 LP receiver (LP RCV)-   45 LP decoder (LP DEC)-   46 LP state machine (LP FSM)-   51 HS state machine (HS FSM)-   52 selector-   53 parallel-serial (PS) conversion circuit-   54 clock frequency divider (DIV)-   55 HS driver (HS DRV)-   56 termination circuit (TERM) (clock signal termination circuit)-   57 HS receiver (HS RCV)-   58 clock frequency divider (DIV)-   59 clock (CL) state discrimination circuit-   61 LP state machine (LP FSM)-   62 LP encoder (LP ENC)-   63 LP driver (LP DRV)-   64 LP receiver (LP RCV)-   65 LP decoder (LP DEC)-   66 LP state machine (LP FSM)-   71 HS state machine (HS FSM)-   72 selector-   73 parallel-serial (PS) conversion circuit-   74 HS driver (HS DRV)-   75 termination circuit (TERM) (data signal termination circuit)-   76 HS receiver (HS RCV)-   77 clock frequency divider (DIV)-   78 word alignment correction circuit (ALN)-   81 PLL circuit-   82 crystal oscillator (XTAL)-   83 crystal oscillator (XTAL)-   84 PLL circuit-   101 transmitter-   102 receiver-   111 CL-HS circuit-   112 CL-LP circuit-   113 DL-HS circuit-   114 DL-LP circuit-   121 CL-HS circuit-   122 CL-LP circuit-   123 DL-HS circuit-   124 DL-LP circuit-   300 smartphone-   301 vehicle-   302 ECU-   310 application processor-   311 CPU-   312 memory controller-   313 power source controller-   314 external interface-   315 GPU-   316 media processor-   317 display controller-   318 media processor-   319 system bus-   401, 402, 403, 404 vehicle-mounted camera-   410 image sensor-   411 sensor-   412 ISP-   413 JPEG encxler-   414 CPU-   415 RAM-   416 ROM-   417 power source controller-   418 PC interface-   419 MIPI interface-   420 system bus-   431 image sensor-   432 DSP circuit-   433 selector-   434 SerDes circuit-   441 connection interface-   442 connection interface-   501 memory-   502 wireless communication section-   504 display-   AP application processor-   IS image sensor-   TX transmitter-   RX receiver-   Dp signal line-   Dn signal line-   CL clock lane-   DL, DL1, DL2, DL3, DL4 data lane

1. A reception device comprising: a data signal receiver circuitconfigured to receive a data signal and a data blanking signal from atransmission device that is operating in one of a plurality ofcommunication modes, the data blanking signal is received during ablanking period of the data signal; a clock signal receiver circuitconfigured to receive a clock signal and a clock blanking signal that isin synchronization with the blanking period of the data signal from thetransmission device; and a determination circuit configured to determinethat the transmission device is operating in the one of the plurality ofcommunication modes on a basis of a signal value of the data blankingsignal, a signal value of the clock blanking signal, or both.
 2. Thereception device according to claim 1, wherein a first mode of theplurality of communication modes is a high speed mode, a second mode ofthe plurality of communication modes is a low power mode, and a thirdmode of the plurality of communication modes is one of a high speed idlemode or an alternative low power mode.
 3. The reception device accordingto claim 2, wherein the low power mode comprises a data transmissionspeed that is lower than a data transmission speed of the high speedmode, and the low power mode comprises a voltage level that is differentthan a voltage level of the high speed mode.
 4. The reception deviceaccording to claim 2, further comprising: a terminator, wherein the highspeed idle mode does not have signal activity during the blankingperiod, and responsive to determining that the transmission device isoperating in the high speed idle mode, the data signal receiver circuitis further configured to not perform a termination control of theterminator during the blanking period.
 5. The reception device accordingto claim 2, further comprising: a terminator, wherein the alternativelow power mode does not have signal activity during the blanking period,and responsive to determining that the transmission device is operatingin the alternative low power mode, the data signal receiver circuit isfurther configured to perform a termination control of the terminatorduring the blanking period.
 6. The reception device according to claim2, wherein the data signal transmitted by the transmission deviceoperating in the first mode or the third mode is a differential signal,and the data signal transmitted by the transmission device operating inthe second mode is a single-ended signal.
 7. The reception deviceaccording to claim 2, wherein the clock signal transmitted by thetransmission device operating in the first mode or the third mode is adifferential signal, and the clock signal transmitted by thetransmission device operating in the second mode is a single-endedsignal.
 8. A reception device comprising: a data signal receiver circuitconfigured to receive a data signal from a transmission device thatoperates in a plurality of communication modes via a data lane, theplurality of communication modes including a first mode, a second mode,and a third mode; a clock signal receiver circuit configured to receivea clock signal from the transmission device that operates in theplurality of communication modes via a clock lane; and a determinationcircuit configured to determine that the transmission device isoperating in one of the plurality of communication modes on a basis of asignal value of the data signal and a transition of the clock signal,the transition of the clock signal being indicative of the transmissiondevice transitioning from another mode of the plurality of communicationmodes to the one of the plurality of communication modes.
 9. Thereception device according to claim 8, wherein the first mode is a highspeed mode, the second mode is a low power mode, and the third mode isone of a high speed idle mode or an alternative low power mode.
 10. Thereception device according to claim 9, wherein the transition of theclock signal is indicative of the transmission device transitioning fromthe high speed mode to the low power mode.
 11. The reception deviceaccording to claim 10, wherein the transmission device is alreadyoperating in the low power mode when the transition of the clock signalis indicative of the transmission device transitioning from the highspeed mode to the low power mode.
 12. The reception device according toclaim 9, wherein the transition of the clock signal s indicative of thetransmission device transitioning from the high speed mode to the highspeed idle mode.
 13. The reception device according to claim 12, whereinthe transmission device is already operating in the high speed idle modewhen the transition of the clock signal is indicative of thetransmission device transitioning from the high speed mode to the highspeed idle mode.
 14. The reception device according to claim 9, whereinthe transition of the clock signal is indicative of the transmissiondevice transitioning from the low power mode to the high speed mode. 15.The reception device according to claim 14, wherein the transmissiondevice is not yet operating in the high speed mode when the transitionof the clock signal is indicative of the transmission devicetransitioning from the low power mode to the high speed mode.
 16. Thereception device according to claim 9, wherein the transition of theclock signal is indicative of the transmission device transitioning fromthe high speed idle mode to the high speed mode.
 17. The receptiondevice according to claim 16, wherein the transmission device is not yetoperating in the high speed mode when the transition of the clock signalis indicative of the transmission device transitioning from the highspeed idle mode to the high speed mode.
 18. The reception deviceaccording to claim 8, wherein the clock signal receiver circuit isfurther configured to detect when the clock signal is not received fromthe transmission device via the clock lane during a period of time, andresponsive to detecting that the clock signal is not received from thetransmission device via the clock lane during the period of time, outputa first control signal to the determination circuit, the data signalreceiver circuit is further configured to detect when the signal valueof the data signal is a first value, responsive to detecting when thesignal value of the data signal is the first value, output a secondcontrol signal to the determination circuit, and responsive to detectingwhen the signal value of the data signal is not the first value, outputa third control signal to the determination circuit, the third controlsignal being different than the second control signal, and thedetermination circuit is further configured to receive the first controlsignal, the second control signal, and the third control signal, anddetermine the transmission device is operating in the one of theplurality of communication modes on a basis of receiving the firstcontrol signal and the second control signal or receiving the firstcontrol signal and the third control signal.
 19. The reception deviceaccording to claim 18, wherein the clock signal receiver circuitincludes a counter that is configured to count a second clock signalthat is different than the clock signal, and to detect when the clocksignal is not received from the transmission device via the clock laneduring the period of time, the clock signal receiver circuit is furtherconfigured to control the counter to count a plurality of clocktransitions of the second clock signal that exceeds the period of time.20. A communication system, comprising: a transmission device includinga data signal transmitter circuit configured to operate in a pluralityof communication modes to transmit a data signal via a data lane, andtransmit a data blanking signal in a blanking period of the data signalvia the data lane; a clock signal transmitter circuit configured totransmit a clock signal and a clock blanking signal in synchronizationwith the blanking period of the data signal via a clock lane; and ablanking controller configured to control a signal value of the datablanking signal, a signal value of the clock blanking signal, or both tobe indicative of the one of the plurality of communication modes; and areception device including a data signal receiver circuit configured toreceive the data signal and the data blanking signal from thetransmission device that is operating in the one of the plurality ofcommunication modes via the data lane, the data blanking signal isreceived during the blanking period of the data signal; a clock signalreceiver circuit configured to receive the clock signal and the clockblanking signal that is in synchronization with the blanking period ofthe data signal from the transmission device via the clock lane; and adetermination circuit configured to determine that the transmissiondevice is operating in the one of the plurality of communication modeson a basis of the signal value of the data blanking signal, the signalvalue of the clock blanking signal, or both.
 21. A transmission devicecomprising: a data signal transmitter circuit configured to operate in aplurality of communication modes to transmit a data signal to areception device via a data lane, and transmit a data blanking signal ina blanking period of the data signal to the reception device via thedata lane; a clock signal transmitter circuit configured to transmit aclock signal and a clock blanking signal in synchronization with theblanking period of the data signal to the reception device via a clocklane; and a blanking controller configured to control a signal value ofthe data blanking signal, a signal value of the clock blanking signal,or both to indicate that the data signal transmitter circuit isoperating in the one of the plurality of communication modes.
 22. Thetransmission device according to claim 21, wherein a first mode of theplurality of communication modes is a high speed mode, a second mode ofthe plurality of communication modes is a low power mode, and a thirdmode of the plurality of communication modes is one of a high speed idlemode or an alternative low power mode.
 23. The transmission deviceaccording to claim 22, wherein the low power mode comprises a datatransmission speed that is lower than a data transmission speed of thehigh speed mode, and the low power mode comprises a voltage level thatis different than a voltage level of the high speed mode.
 24. Thetransmission device according to claim 22, wherein the data signaltransmitted by the data signal transmitter circuit operating in thefirst mode or the third mode is a differential signal, the data signaltransmitted by the data signal transmitter circuit operating in thesecond mode is a single-ended signal, the clock signal transmitted bythe clock signal transmitter circuit, when the data signal transmittercircuit is operating in the first mode or the third mode, is adifferential signal, and the clock signal transmitted by the clocksignal transmitter circuit, when the data signal transmitter circuit, isoperating in the second mode is a single-ended signal.
 25. A signalreception method, the method comprising: receiving, with a data signalreceiver of a reception device, a data signal and a data blanking signalfrom a transmission device that is operating in one of a plurality ofcommunication modes via a data lane, the data blanking signal isreceived during a blanking period of the data signal; receiving a clocksignal and a clock blanking signal that is in synchronization with theblanking period of the data signal from the transmission device; anddetermining that the transmission device is operating in the one of theplurality of communication modes on a basis of a signal value of thedata blanking signal, a signal value of the clock blanking signal, orboth.
 26. A signal transmission method, the method comprising:operating, with a data signal transmitter circuit of a transmissiondevice, in one of a plurality of communication modes to transmit a datasignal to a reception device via a data lane; responsive to operating inthe one of the plurality of communication modes, controlling a signalvalue of a data blanking signal, a signal value of a clock blankingsignal, or both to be indicative of the one of the plurality ofcommunication modes; transmitting the data blanking signal to thereception device during a blanking period of the data signal via thedata lane; and transmitting a clock signal and the clock blanking signalin synchronization with the blanking period of the data signal to thereception device via a clock lane.
 27. A communication method, themethod comprising: operating, with a data signal transmitter circuit ofa transmission device, in one of a plurality of communication modes totransmit a data signal via a data lane; responsive to operating in theone of the plurality of communication modes, controlling a signal valueof a data blanking signal, a signal value of a clock blanking signal, orboth to be indicative of the one of the plurality of communicationmodes; transmitting the data blanking signal during a blanking period ofthe data signal via the data lane; transmitting a clock signal and theclock blanking signal in synchronization with the blanking period of thedata signal via a clock lane; receiving, with a data signal receiver ofa reception device, the data signal and the data blanking signal fromthe transmission device that is operating in the one of the plurality ofcommunication modes via the data lane, the data blanking signal isreceived during the blanking period of the data signal; receiving theclock signal and the clock blanking signal that is in synchronizationwith the blanking period of the data signal from the transmissiondevice; and determining that the transmission device is operating in theone of the plurality of communication modes on a basis of the signalvalue of the data blanking signal, the signal value of the clockblanking signal, or both.